Design method estimating signal delay time with netlist in light of terminal line in macro, and program
AssigneeNEC Electronics Corporation
InventorAkihiro Asahina
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AssigneeNEC Electronics Corporation
InventorAkihiro Asahina
Estimating the term…
A design method according to an aspect of the present invention includes laying out a plurality of functional blocks of a design circuit based on a first netlist, creating a second netlist by adding a first path information to the first netlist, the first path information corresponding to an inter-block line connecting between the functional blocks, creating a third netlist by adding a second path information to the second netlist, the second path information corresponding to an intra-block line connected to a terminal of each functional block from inside of each functional block, creating a fourth netlist that models a line resistance and a line capacitance of an inter-instance line which combines the first path information and the second path information included in the third netlist, and estimating a delay time from information based on the fourth netlist.
A design method implementing automatic layout based on a first netlist created from a design circuit, comprising:
A computer program product, in a computer readable medium, that causes a computer to execute estimation calculation of signal delay time in a design circuit, comprising instructions for:
A netlist manipulation program that causes a computer to execute creation of a netlist used for calculation of signal delay time in a design circuit, the netlist manipulation program comprising:
Dependencies are inferred from the claim text.