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US 2009/0215202 A1Published application
Controlled edge resistivity in a silicon wafer
AssigneeSiltronic AG
InventorsKevin Lite, Quynh Tran
Life of this patent
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Abstract
An epitaxial silicon wafer is produced with a resistivity in the area adjacent the edge that is greater or less than the resistivity adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge resistivity. Such process parameters may include using a non-homogeneous temperature and/or a process reactant gas flow across the front surface of the wafer.
Claims5
A method for manufacturing a silicon wafer, each wafer defining a center, a circular outer edge, an area adjacent the edge, and a front surface, the method comprising:
- depositing an epitaxial layer over the front surface of the wafer, the layer having a first resistivity adjacent the center, and a second resistivity in the area adjacent the edge,
- adjusting, during the step of depositing the epitaxial layer, at least one process parameter to control the second resistivity to be changed by at least about 2% compared to the first resistivity.
Dependencies are inferred from the claim text.