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US 2009/0214843 A1Published application
Controlled edge resistivity in a silicon wafer
AssigneeSiltronic AG
InventorsKevin Lite, Quynh Tran
Life of this patent
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Abstract
An epitaxial silicon wafer is provided with a thickness in the area adjacent the edge that is greater or less than the thickness adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge thickness.
Claims12
A silicon wafer defining a center, an edge, and an area adjacent the edge, the wafer including an epitaxial layer, the wafer comprising:
- a first thickness of the epitaxial layer adjacent the center, and
- a second thickness of the epitaxial layer in the area adjacent the edge, wherein the second thickness is changed by at least about 2% compared to the first thickness.
A method for manufacturing a silicon wafer, each wafer defining a center, a circular outer edge, an area adjacent the edge, and a front surface, the method comprising:
- depositing an epitaxial layer over the front surface of the wafer, the layer having a first thickness adjacent the center, and a second thickness in the area adjacent the edge.
- adjusting, during the step of depositing the epitaxial layer, at least one process parameter to control the second thickness to be changed by at least about 2% compared to the first thickness.
Dependencies are inferred from the claim text.