Back to results
US 2009/0214026 A1Published application
Method and apparatus for optimizing advanced encryption standard (aes) encryption and decryption in parallel modes of operation
AssigneeIntel Corporation
InventorsShay Gueron, Amit Gradstein, Zeev Sperber
Life of this patent
Estimating the term…
Abstract
The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
Claims18
A method comprising:
- performing an Advanced Encryption Standard (AES) operation on a plurality of fixed size blocks using a mode of operation that operates on a block independently of other blocks comprising:
- storing a set of k consecutive blocks of the plurality of fixed sized blocks in k registers, k greater or equal to the latency (L) of an AES round instruction, the AES round instruction to perform a sequence of AES round operations for an AES round on the block;
- and
- performing the sequence of AES round operations on the set of k consecutive blocks in parallel by dispatching one AES round instruction per cycle for each of the k blocks.
1 more element
An apparatus comprising:
- a register file to store a set of k consecutive blocks of the plurality of fixed sized blocks in k registers, k greater or equal to the latency (L) of an AES round instruction, the AES round instruction to perform a sequence of AES round operations for the round on the block;
- and
- an execution unit to perform an Advanced Encryption Standard (AES) operation on a plurality of fixed size blocks using a mode of operation that operates on a block independently of other blocks, the execution unit to perform the sequence of AES round operations on the set of k consecutive blocks in parallel by dispatching one AES round instruction per cycle for each of the k blocks.
An article including a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:
- performing an Advanced Encryption Standard (AES) operation on a plurality of fixed size blocks using a mode of operation that operates on a block independently of other blocks comprising:
- storing a set of k consecutive blocks of the plurality of fixed sized blocks in k registers, k greater or equal to the latency (L) of an AES round instruction, the AES round instruction to perform a sequence of AES round operations for an AES round on the block;
- and
- performing the sequence of AES round operations on the set of k consecutive blocks in parallel by dispatching one AES round instruction per cycle for each of the k blocks.
1 more element
Dependencies are inferred from the claim text.