Low-power register array for fast shift operations

Abstract

A data register (300) for use in a computer comprises a clock terminal (310) configured to receive a clock signal. A plurality of registers (320) are configured to selectively store data. A data input circuit (330) is coupled to the registers and configured to receive input data and selectively deliver the input data to the registers. A data output circuit (340) is coupled to the data registers and configured to selectively output the output data. A selector (350) is coupled to the data input circuit and the data output circuit, and configured to permit the input data it enter selected registers through the data input circuit and permit selected registers to output data through the data output circuit. The invention provides an efficient technique for loading the shift registers without a large number of simultaneous serial shifts. The result is a power-efficient that achieves high performance objectives while minimizing power consumption.

Dependencies are inferred from the claim text.