US 2009/0213973 A1 · CLOCK REGENERATION CIRCUIT

Abstract

A clock regeneration circuit according to the present invention that generates a clock signal that is synchronized to an input signal, includes: a detection section which detects points at which the input signal transitions; a histogram generation section which associates a plurality of partial periods with the transition points, and generates a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal; a calculation processing section which generates a second histogram by calculation processing based on the first histogram, and calculates a phase adjustment value of the clock signal based on the second histogram; and a phase adjustment section which adjusts a phase of the clock signal based on the phase adjustment value.

Claims18

Dependent claims

A clock regeneration circuit that generates a clock signal that is synchronized to an input signal, comprising:

a detection section which detects points at which the input signal transitions;
a histogram generation section which associates a plurality of partial periods with the transition points, and generates a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal;
a calculation processing section which generates a second histogram by calculation processing based on the first histogram, and calculates a phase adjustment value of the clock signal based on the second histogram;
and
a phase adjustment section which adjusts a phase of the clock signal based on the phase adjustment value.

2 more elements

A clock regeneration circuit that generates a clock signal that is synchronized to an input signal, comprising:

detection means for detecting points at which the input signal transitions;
histogram generation means for associating a plurality of partial periods with the transition points, and generating a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal;
calculation processing means for generating a second histogram by calculation processing based on the first histogram, and calculating a phase adjustment value of the clock signal based on the second histogram;
and
phase adjustment means for adjusting a phase of the clock signal based on the phase adjustment value.

2 more elements

A clock regeneration method for generating a clock signal that is synchronized to an input signal, comprising:

detecting points at which the input signal transitions;
associating a plurality of partial periods with the transition points, and generating a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal;
generating a second histogram by calculation processing based on the first histogram, and calculating a phase adjustment value of the clock signal based on the second histogram;
and
adjusting a phase of the clock signal based on the phase adjustment value.

2 more elements

Dependencies are inferred from the claim text.

Clock regeneration circuit

Life of this patent

Clock regeneration circuit

Life of this patent

Abstract

Claims18