Power-saving method for viterbi decoder and bit processing circuit of wireless receiver
AssigneeRalink Technology Corporation
InventorShih-Yi Yeh
Life of this patent
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Abstract
A power-saving method for Viterbi decoder and bit processing circuit of wireless receiver is provided. In response to various computational load of bit processing circuit and/or Viterbi decoder of a wireless receiver, the method is used for adjusting duty cycle of the bit processing circuit and/or the Viterbi decoder so as to save power in addition, in response to various data rates of the wireless receiver, the Viterbi decoder and the bit processing circuit are provided with power based on various duty cycles of related time pulse signals, thereby preventing the Viterbi decoder and/or the bit processing circuit from consuming power while being idle (during time segments of idle operation), so as to reduce power consumption.
Claims19
A power-saving method for Viterbi decoder of a wireless receiver, comprising the steps of:
- determining at least one numerical value related to a data rate applied by the wireless receiver while receiving packet;
- and
- deciding a duty cycle of the Viterbi decoder based on the at least one numerical value, wherein power is provided to the Viterbi decoder based on the duty cycle.
A power-saving method for a bit processing circuit of a wireless receiver, wherein the wireless receiver has a time pulse circuit for outputting a time pulse signal, and the time pulse single controls the bit processing circuit to perform bit processing of the wireless receiver, comprising the steps of:
- determining a data rate applied by the wireless receiver while receiving packet;
- and
- deciding a duty cycle of the time pulse signal based on the data rate,
- wherein power is provided to the bit processing circuit based on the duty cycle of the time pulse signal.
Dependencies are inferred from the claim text.