Internal Loop-Back Architecture For Parallel Serializer/Deserializer (SERDES)

An internal loop-back architecture for a parallel serializer/deserializer (SERDES), comprising:

• a plurality of transmitters arranged in a parallel architecture in which adjoining transmitters can communicate with each other;
• and
• a plurality of receivers arranged in a parallel architecture in which adjoining receivers can communicate with each other, wherein at least a portion of the transmitters and a portion of the receivers share a communication channel and wherein any of the plurality of transmitters in a row can communicate with any of the plurality of receivers in a row, and wherein each of the plurality of transmitters includes a loop-back arrangement with each of the plurality of receivers.

A method for performing internal loop-back testing on a serializer/deserializer (SERDES), comprising:

• coupling a plurality of transmit elements arranged in a parallel architecture with a plurality of receive elements arranged in a parallel architecture such that at least a portion of the transmit elements and a portion of the receive elements share a communication channel and such that any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and such that each of the plurality of transmit elements includes a loop-back arrangement with each of the plurality of receive elements.