Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of memory cells each including a source, a drain, and a floating body in an electrically floating state, the memory cells storing logic data based on number of carriers within the floating body;
• a plurality of bit lines connected to the drains;
• a plurality of word lines crossing the bit lines, the word lines functioning as gates of the memory cells or being connected to gates of the memory cells;
• a plurality of source lines connected to the sources, and extended along the word lines;
• sense amplifiers detecting data stored in the memory cells;
• and
• drivers driving the word lines or the source lines, wherein
• in the first cycle of driving the selected word line out of the word lines and the selected source line out of the source lines, the drivers write the first logic data showing the state of a large number of the carriers to the memory cells connected to the selected word line and the selected source line, and
• in the second cycle of driving the selected bit line out of the plurality of bit lines, the sense amplifiers write the second logic data showing the state of a small number of the carriers selectively to the memory cells connected to the selected bit line out of the memory cells into which the first logic data is written in the first cycle.

A semiconductor memory device comprising:

• a plurality of memory cells each including a source, a drain, and a floating body in an electrically floating state, the memory cells storing logic data based on number of carriers within the floating body;
• a plurality of bit lines connected to the drains;
• a plurality of word lines crossing the bit lines, the word lines functioning as gates of the memory cells or being connected to gates of the memory cells;
• a plurality of source lines connected to the sources, and extended along the word lines;
• sense amplifiers detecting data stored in the memory cells;
• drivers driving the word lines or the source lines;
• a counter cell array including a plurality of counter cells provided corresponding to the word lines, the counter cell array storing number of activation of the word lines;
• and
• an adder circuit incrementing the number of activation of the selected word line, at each time of reading or writing data from or to the memory cells, wherein
• adjacent a first and a second word lines out of the word lines are provided corresponding to one of the sources or one of the drains, and
• when the number of activation of the first word line becomes a predetermined value, the adder circuit outputs an instruction to perform a refresh operation of the memory cells connected to the second word line, the refresh operation recovering logic data stored in the memory cells.