Method and device for controlling a memory access and correspondingly configured semiconductor memory

A method for manufacturing a device for controlling a memory access of a memory,

• wherein the memory comprises memory cells,
• wherein the memory access is a reading operation or a writing operation of the memory,
• wherein the method comprises:
• providing at least one dummy bit line, at least one dummy word line and a detection device,
• configuring the detection device to determine a completion of the memory access by means of the at least one dummy bit line,
• connecting each of a plurality of memory cells of said memory cells to the at least one dummy bit line and to the at least one dummy word line,
• configuring the device such that the at least one dummy bit line is connected to said plurality of memory cells such that a content of said plurality of memory cells is readable via the at least one dummy bit line, and
• connecting said plurality of memory cells such that each of said plurality of memory cells is settable to a predetermined potential by the device.

A device for controlling a memory access of a memory,

• wherein the memory comprises memory cells,
• wherein the memory access is a reading operation or a writing operation of the memory,
• wherein the device comprises at least one dummy bit line, at least one dummy word line and a detection device,
• wherein the detection device is configured to determine a completion of the memory access by means of the at least one dummy bit line,
• wherein the device is configured such that each of a plurality of memory cells of said memory cells is connected to the at least one dummy bit line and to the at least one dummy word line,
• wherein the device is configured such that the at least one dummy bit line is connected to said plurality of memory cells such that a content of said plurality of memory cells is readable via the at least one dummy bit line, and
• wherein said plurality of memory cells is connected such that each of said plurality of memory cells is settable to a predetermined potential by the device.

A semiconductor memory comprising a device for controlling a memory access of a memory,

• wherein the memory comprises memory cells,
• wherein the memory access is a reading operation or a writing operation of the memory,
• wherein the device comprises at least one dummy bit line, at least one dummy word line and a detection device,
• wherein the detection device is configured to determine a completion of the memory access by means of the at least one dummy bit line,
• wherein the device is configured such that each of a plurality of memory cells of said memory cells is connected to the at least one dummy bit line and to the at least one dummy word line,
• wherein the device is configured such that the at least one dummy bit line is connected to said plurality of memory cells such that a content of said plurality of memory cells is readable via the at least one dummy bit line, and
• wherein said plurality of memory cells is connected such that each of said plurality of memory cells is settable to a predetermined potential by the device.