Circuit and method for controlling redundancy in semiconductor memory apparatus

A circuit for controlling redundancy in a semiconductor memory apparatus, the circuit comprising:

• a fuse set unit which compares a first latch address, which is obtained by buffering and latching an external address, with an output signal of each fuse circuit to generate a repair determination signal;
• a global address generating unit which receives a second latch address, which is obtained by buffering and latching the external address, and the output signal of each fuse circuit of the fuse set unit to generate a global address based on the repair determination signal, a first internal command, and a refresh signal;
• a local address generating unit which generates a local address from the global address corresponding to a second internal command;
• a redundant decoding unit which activates a redundancy word line in accordance to indication of the local address;
• and
• a main decoding unit which activates a main word line in accordance to the indication of the local address.

A method for controlling redundancy in a semiconductor memory apparatus, the method comprising:

• comparing an address delivered from an exterior and an output signal of a plurality of fuse circuits having preset fuse short information to generate a repair determination signal;
• receiving a first latch address, which is obtained by buffering and latching an external address with the output signal of each fuse circuit of a fuse set unit to generate a global address in accordance to the repair determination signal, a first internal command, and a refresh signal;
• generating a local address from the global address corresponding to input of a second internal command;
• and
• activating a redundancy word line or a main word line in accordance to indication of the local address,
• wherein the global address includes information about a repair operation state,
• wherein the generating of the repair determination signal and the global address are performed in a peripheral area,
• and wherein the generating of the local address and the activating of the redundancy word line or the main word line are performed in a memory bank area.