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US 2009/0213670 A1Published application
Asynchronous, high-bandwidth memory component using calibrated timing elements
AssigneeRambus Inc.
InventorsFrederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark
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Abstract
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
Claims1
A method of operation within an asynchronous dynamic random access memory (DRAM) device, the method comprising:
- receiving a command, an input load signal and a delay-select value;
- storing the delay-select value within a register;
- retrieving read data from a memory core in response to the command;
- and
- asserting a register-load signal a predetermined time after receipt of the input load signal to enable the read data to be output from the asynchronous memory device, wherein the predetermined time includes a delay interval having a duration selected by the delay-select value.
2 more elements
Dependencies are inferred from the claim text.