# US 2009/0213662 A1 · Memory device and applications thereof

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- Number: US 2009/0213662 A1
- Document ID: US20090213662A1
- Status: Published application
- Kind: A1
- Application number: 12/391,651
- Filed: 2009-02-24
- Published: 2009-08-27
- Earliest claimed: 2008-02-25
- Assignees: The Board of Trustees of the University of Illinois
- Inventors: Jean-Pierre Leburton; Jeanlex Soares de Sousa; Gil De Aquino Farias; Valder Nogueira Freire
- Web page: https://patentgrep.com/patent/US20090213662A1

## CPC

- G11C 13/047: {using electro-optical elements (G11C13/042 takes precedence)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 2216/06: Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
- Y10S 977/773: Nanoparticle, i.e. structure having three dimensions of 100 nm or less
- Y10S 977/954: Of radiant energy
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A system that incorporates teachings of the present disclosure may include, for example, a memory device having a memory cell to selectively store holes by photon and bias voltage induction as a representation of binary values. Additional embodiments are disclosed.

## Claims

### Claim 1

A memory device, comprising:
an n-type doped silicon substrate;
a tunnel oxide layer formed on the n-type doped silicon substrate;
a floating nanocrystal gate embedded in a control oxide layer and formed on the tunnel oxide layer;
a drain region formed by implantation of a p-type dopant material in the n-type silicon substrate;
a source region formed by implantation of a p-type dopant material in the n-type silicon substrate;
a photon source coupled to the floating nanocrystal gate; and
a control gate formed on the control oxide layer,
wherein a first memory state is produced by:
applying photons generated by the photon source to the floating nanocrystal gate to induce electron-hole pairs, and
applying one or more bias voltages to at least one among the control gate, the drain region and the source region to induce a removal of electrons from the floating nanocrystal gate.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the photons have energies at or near a bandgap of the floating nanocrystal gate.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the photons have energies in an infrared region of a light spectrum.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the one or more bias voltages comprise at least a negative bias voltage applied to the control gate to induce the removal of electrons from the floating nanocrystal gate and the retention of holes in the floating nanocrystal gate, thereby producing the first memory state.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the photon source applies photons to the floating nanocrystal gate for a time period that produces a desired density range of electron-hole pairs, wherein the photon source stops applying photons to the floating nanocrystal gate when the time period expires, and wherein the one or more bias voltages are applied after the application of photons ceases.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein a second memory state is produced by applying one or more bias voltages of opposing polarity to the one or more bias voltages that produced the first memory state.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the one or more bias voltages of opposing polarity comprise at least a positive bias voltage applied to the control gate to inject electrons into the floating nanocrystal gate which removes holes in the floating nanocrystal gate, thereby producing the second memory state.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the photon source comprises at least one of a laser and a light emitting diode.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the floating nanocrystal gate comprises a layer of at least one nanocrystal embedded in the control oxide layer, and wherein the at least one nanocrystal comprises a silicon germanium alloy.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein increasing a size of the at least one nanocrystal increases a retention time of holes accumulated thereby.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein an accumulation of holes in the floating nanocrystal gate represents a first binary value, and wherein a deficiency of holes in the floating nanocrystal gate represents a second binary value.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein the tunnel oxide layer or the control oxide layer comprises hafnium oxide.

### Claim 13

A memory device, comprising a memory cell to selectively store holes by photon and bias voltage induction as a representation of binary values.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein an accumulation of holes in the memory cell represents a first binary value, and wherein a deficiency of holes in the memory cell represents a second binary value.

### Claim 15 (depends on 13)

The memory device of claim 13, wherein the memory cell comprises a p-channel transistor with at least one floating nanocrystal gate coupled to a photon source.

### Claim 16 (depends on 13)

The memory device of claim 13, wherein the memory cell comprises:
an n-type substrate;
a tunnel oxide layer formed on the n-type substrate;
a floating nanocrystal gate embedded in a control oxide layer formed on the tunnel oxide layer coupled to a photon source; and
a control gate formed on the control oxide layer.

### Claim 17

A memory device, comprising an array of memory cells, each memory cell selectively stores holes by photon and bias voltage induction as a representation of binary values.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the memory device is a random access memory device.

### Claim 19 (depends on 17)

The memory device of claim 17, wherein the array comprises one among a NOR memory array and a NAND memory array.

### Claim 20 (depends on 17)

The memory device of claim 17, wherein the array comprises at least one decoder to perform read and write cycles.

### Claim 21 (depends on 17)

The memory device of claim 17, wherein an accumulation of holes in each memory cell represents a first binary value, and wherein a deficiency of holes in each memory cell represents a second binary value.

### Claim 22 (depends on 17)

The memory device of claim 17, wherein each memory cell comprises a p-channel transistor with at least one floating nanocrystal gate coupled to a photon source.

### Claim 23 (depends on 17)

The memory device of claim 17, wherein each memory cell comprises:
an n-type substrate;
a tunnel oxide layer formed on the n-type substrate;
a floating nanocrystal gate embedded in a control oxide layer formed on the tunnel oxide layer coupled to a photon source; and
a control gate formed on the control oxide layer.

### Claim 24 (depends on 17)

The memory device of claim 17, wherein the memory device is a non-volatile memory device.

### Claim 25 (depends on 17)

The memory device of claim 17, wherein the memory device comprises a mass storage medium utilized by a computer.

### Claim 26

An apparatus, comprising:
a memory array to selectively store holes by photon and bias voltage induction; and
a computing device coupled to the memory array.

### Claim 27 (depends on 26)

The apparatus of claim 26, wherein the apparatus comprises one among a computer, an automobile, a portable memory device, a telephony device, an appliance, a set-top box, and a television set, and wherein the computing device comprises one among a microprocessor, and a digital signal processor.