Flash memory device and flash memory system including the same

A flash memory device comprising:

• a memory cell array;
• a control logic circuit configured to discriminate a data input/output cycle into one of an address latch cycle, a command latch cycle, an input data latch cycle, and a data output cycle with reference to a combination of an address latch enabling signal and a command latch enabling signal;
• a reading/programming circuit controlled by the control logic circuit, reading data from the memory cell array in a reading operation and programming data into the memory cell array in a programming operation;
• a signal generator delaying a first data fetch signal and outputting a second data fetch signal if the data input/output cycle is determined as the data output cycle;
• and
• an output buffer circuit sequentially outputting data of the reading/programming circuit in sync with rising and falling edges of the second data fetch signal if the data input/output cycle is determined as the data output cycle,
• wherein the second data fetch signal is output externally along with data output from the output buffer circuit.

A flash memory system comprising:

• a flash memory device;
• and
• a memory controller configured to control the flash memory device,
• wherein the flash memory device generates a second data fetch signal from a first data fetch signal provided from the memory controller in a reading operation and outputs read data to the memory controller in sync with the second data fetch signal, wherein the second data fetch signal is transferred to the memory controller along with the read data.