Memory system with user configurable density/performance option
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple memory blocks. The different memory blocks of each die can be assigned a different memory density by the end user, depending on the desired memory performance and/or memory density. The user configurable density/performance option can be adjusted with special read/write operations or a configuration register having a memory density configuration bit for each memory block.
Claims25
A memory system comprising:
- a system controller for generating density configuration bits for the memory system, the system controller configured to access a table in memory that stores the density configuration with an associated function of the memory;
- and
- a plurality of memory dies coupled to the processor, each die having selectable density configurations and comprising:
- a memory array comprising a plurality of memory cells that are organized into sets of memory cells, each memory cell configured to store a selectable quantity of data bits;
- control circuitry, coupled to the memory array and the system controller, for configuring the density configurations of the sets of memory cells in response to the density configuration bits and the table;
- and
- a configuration register, coupled to the control circuitry, for storing the density configuration bits.
A memory system comprising:
- a system controller for generating a density configuration for the memory system, the system controller configured to read a table in memory that stores the density configuration with each associated user input;
- and
- a plurality of memory dies coupled to the system controller, each die comprising:
- a memory array comprising a plurality of memory cells that are organized into memory cell groupings, each memory cell grouping configured to store a selectable density of data bits;
- and
- control circuitry, coupled to the memory array and the system controller, that is configured to select the density of data bits in response to the density configuration generated from the table in memory.
A memory device comprising:
- a plurality of memory cells organized in memory cell groupings, each memory cell configured to store a selectable quantity of data bits;
- and
- memory control circuitry coupled to the plurality of memory cells and configured to determine if a received command is one of a high or low performance configuration write command or a high or low performance configuration read command, the controller further configured to execute the received command responsive to the high or low performance configuration.
A method for configuring memory density of a memory array, the method comprising:
- generating configuration data by reading a table in memory that comprises configuration data associated with each user input;
- storing the configuration data into a configuration register;
- and
- setting the memory density for at least a subset of the memory array in response to the configuration data.
A method for configuring memory performance of a memory array, the method comprising:
- obtaining a desired memory performance configuration by accessing a table in memory;
- and
- configuring a grouping of memory cells of the memory array in response to the desired memory performance configuration.
The method of 16 wherein obtaining the desired memory performance configuration further includes receiving an input from a user.
A method for configuring a density/performance of a memory device having at least one grouping of memory cells, the method comprising:
- determining a density/performance configuration bit for each grouping of memory cells in response to received performance parameters wherein the configuration bit is determined from a table in memory that stores performance parameters each with an associated configuration bit;
- storing each density/performance configuration bit into a configuration register corresponding to each grouping of memory cells;
- receiving a command to perform one of a read or a write operation on a first grouping of memory cells;
- reading the configuration bit corresponding to the first grouping of memory cells;
- and
- executing the received command on the first grouping of memory cells responsive to the configuration bit.
Dependencies are inferred from the claim text.