Two-bit non-volatile flash memory cells and methods of operating memory cells
AssigneeMacronix International Co., Ltd.
InventorChao-I WU
Life of this patent
Estimating the term…
Abstract
A method for erasing a plurality of two-bit memory cells, each two-bit memory cell comprises a first bit and a second bit. A reference voltage is applied to a first bit line and a second bit line, the first bit line being associated with the first bits of each two-bit memory cell and the second bit line associated with the second bits of each two-bit memory cell. Then a control activation voltage is applied to a first bit line select and a second bit line select, each bit line associated with the first bits and the second bits of each memory cell, respectively. Then an operating voltage is applied to a plurality of word lines associated with each two-bit memory cell, wherein the operating voltage is between 14 and 20 volts.
Claims18
A method of operating a memory device, the method comprising:
- erasing a plurality of two-bit memory cells, each two-bit memory cell comprising a first bit and a second bit, by:
- applying a reference voltage to a first bit line and a second bit line, the first bit line associated with the first bits of each two-bit memory cell and the second bit line associated with the second bits of each two-bit memory cell;
- applying a control activation voltage to a first bit line select and a second bit line select, the first bit line select associated with the first bits of each memory cell and the second bit line select associated with the second bits of each memory cell;
- and
- applying an operating voltage to a plurality of word lines associated with each two-bit memory cell, wherein the operating voltage is between 14 and 20 volts.
The method of 4, wherein the word line activation voltage is between 3 and 8 volts.
The method of 9, wherein the control activation voltage is between 4 and 11 volts.
The method of 10, wherein the read voltage is within an operational window, the operational window being the difference between a programmed voltage threshold level created in a program operation and an erased threshold voltage level created in the erasing of the plurality of two-bit memory cells.
The method of 11, wherein the read voltage is between 0 and 5 volts.
A memory array comprising:
- a semiconductor substrate;
- a plurality of two-bit memory cells having a first and a second source/drain regions set in the semiconductor substrate, each memory cell including a dielectric trapping layer for storing charge, the dielectric trapping layer disposed between a first oxide layer over the semiconductor substrate and a gate layer over the first oxide layer;
- a plurality of word lines coupled to the gate layer;
- a gate voltage source coupled to the plurality of word lines and configured to apply operating voltages between 14 and 20 volts to the plurality of word lines;
- a plurality of bit lines disposed substantially perpendicular to the plurality of word lines, the plurality of bit lines in electrical communication with the first and the second source/drain regions of the plurality of two-bit memory cells;
- and
- a plurality of bit line control cells disposed at the beginning and end of each bit line of the plurality of bit lines, the bit line control cells being configured to control the electrical communication of each bit line with the first and the second source/drain regions of the plurality of two-bit memory cells.
Dependencies are inferred from the claim text.