Integrated Circuit Comprising a Thyristor and Method of Controlling a Memory Cell Comprising a Thyristor

A method for controlling a memory cell with a thyristor structure including a body, a first terminal connected to a respective bit line, and a second terminal connected to a respective word line, the method comprising:

• writing the memory cell by setting the body to a first body potential of at least two different body potentials, wherein the thyristor structure is in a blocking mode with the different body potentials and the different body potentials are descriptive for different memory states;
• and
• reading the memory cell by applying a combination of voltage signals at the terminals, wherein the combination of voltage signals is configured to trigger the corresponding thyristor structure into a conducting mode or a blocking mode depending on the body potential of the corresponding thyristor structure.

A method for controlling a memory cell, the memory cell comprising a thyristor structure with a body, a gate terminal, a cathode terminal and an anode terminal, the method comprising:

• writing a first body potential of at least two different body potentials into the body, wherein the different body potentials are descriptive for different memory states;
• and
• reading the different body potentials by applying a combination of voltage signals at the terminals, wherein the combination of voltage signals is configured to trigger a thyristor structure with at least one of the different body potentials into a conducting mode.

A method for controlling a memory cell, the memory cell including a thyristor structure with a gate terminal, a cathode terminal and an anode terminal, the method comprising:

• triggering the thyristor structure into a conducting mode by applying a first positive voltage at the anode terminal and a second positive voltage at the gate terminal;
• and
• writing a first body potential in the body by reducing the voltage at the gate terminal, wherein the voltages are defined with respect to the cathode terminal.