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US 2009/0213645 A1Published application
Method and apparatus for accessing a multi-mode programmable resistance memory
AssigneeOvonyx, Inc.
InventorsWard Parkinson, Stefan Lai
Life of this patent
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Abstract
A memory is configurable among a plurality of operational modes and types of interfaces. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix. Individual operational modes may be matched to individual interfaces, operated one at a time or in parallel.
Claims56
An apparatus, comprising:
- a plurality of programmable resistance memory cells,
- each cell capable of operating in one of at least two different storage modes;
- a mode controller configured to accept input regarding a selected storage mode and to indicate to memory access circuitry the selected storage mode, the memory access circuitry configured to access the memory cells according to the selected storage mode;
- and
- an interface configured to further access the memory in conformance with a standard interface.
2 more elements
An electronic device, comprising:
- a plurality of programmable resistance memory cells, each cell capable of operating in one of at least two different storage modes;
- a mode controller configured to accept input regarding a selected storage mode and to indicate to memory access circuitry the selected storage mode, the memory access circuitry configured to access the memory cells according to the selected storage mode;
- an interface configured to further access the memory in conformance with a standard interface;
- and
- a microprocessor configured to initiate access of the mode selected memory cell.
2 more elements
A method, comprising the steps of:
- encoding data according to at least one of a plurality of a storage modes provided by a plurality of programmable resistance memory cells;
- storing the encoded data in programmable resistance memory cells;
- and
- accessing the memory cells in conformance with a standard interface.
1 more element
An apparatus, comprising:
- a first segment of a programmable resistance memory comprising a plurality of programmable resistance memory cells, the cells employing a first programmable resistance alloy;
- and
- a second segment of programmable resistance memory comprising a plurality of programmable resistance memory cells, the cells employing a second programmable resistance alloy.
A method comprising the steps of:
- forming a programmable resistance memory having a plurality of segments;
- forming at least one of said segments using a first programmable resistance memory alloy;
- and
- forming at least one of said segments using a second programmable resistance memory alloy.
1 more element
Dependencies are inferred from the claim text.