Memory with active mode back-bias voltage control and method of operating same
OwnerHeechoul Park, Song Chin Kim +2inventors
InventorsHeechoul Park, Song Chin Kim, Lancelot Y. Kwong, Wilson Fai Chin
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Abstract
Data storage cells of a static random access memory array are selectively provided with back-bias voltages to reduce current leakage during an active mode of operation. Circuitry electrically connected with the array receives control signals and provides the back-bias voltages to certain idle data storage cells of the array based on the control signals.
Claims17
An electronic memory device comprising:
- an array of memory storage cells collectively operable in an active mode and a standby mode, at least one of the memory storage cells being accessed during the active mode and the memory storage cells being idle during the standby mode;
- and
- circuitry to provide a back-bias voltage to at least one of the memory storage cells of the array during the active mode.
A static random access memory array comprising:
- a plurality of data cells;
- and
- circuitry being configured to provide a back-bias voltage to one of the plurality of data cells while another of the plurality of data cells is being accessed.
A method for reducing leakage current in a static random access memory array including a plurality of memory storage cells, the method comprising:
- providing a back-bias voltage to one of the plurality of memory storage cells while another one of the plurality of memory storage cells is being accessed thereby reducing leakage current in the one memory storage cell.
Dependencies are inferred from the claim text.