Resistance change memory device
AssigneeKabushiki Kaisha Toshiba
InventorHaruki TODA
Life of this patent
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Abstract
A resistance change memory device including a memory cell array with first wirings, second wirings, and memory cells, the memory cell including a diode and a variable resistance element, anode of diodes being located on the first wiring side, wherein the memory cell array is sequentially set in the following three states after power-on: a waiting state defined by that both the first and second wirings are set at a first voltage; a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively.
Claims17
A resistance change memory device comprising:
- a memory cell array, which includes a plurality of first wirings, a plurality of second wirings so disposed as to cross the first wirings, and memory cells disposed at the cross points of the first and second wirings, the memory cell including a diode and a variable resistance element connected in series, the diode being disposed with such a polarity that anode thereof is located on the first wiring side, wherein
- the memory cell array is sequentially set in the following three states after power-on:
- a waiting state defined by that both the first and second wirings are set at a first voltage;
- a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage;
- and an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively, a selected memory cell being read or written in the access state.
A resistance change memory device comprising:
- a memory cell array, which includes a plurality of first wirings, a plurality of second wirings so disposed as to cross the first wirings, and memory cells disposed at the cross points of the first and second wirings, the memory cell including a diode and a variable resistance element connected in series, the diode being disposed with such a polarity that anode thereof is located on the first wiring side;
- and
- a defect detection circuit configured to detect a defective second wiring, to which a defective cell with a degraded diode is coupled, in such a standby state of the memory cell array that the diodes of the memory cells are reverse-biased, and set the defective second wiring in a floating and unused state.
Dependencies are inferred from the claim text.