Stacked memory and fuse chip
AssigneeElpida Memory, Inc.
InventorKayoko SHIBATA
Life of this patent
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Abstract
A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells. The fuse chip has a fuse unit including a plurality of fuse elements whose electrical cut state corresponding to a replacement with the spare memory cells can be set. Also the fuse chip has a redundancy cell control circuit for controlling a redundancy cell operation of the defective memory cells based on state information of the fuse unit.
Claims15
A stacked memory comprising:
- one or more memory core chips, each of the chips having a memory cell array including spare memory cells replacing defective memory cells;
- and
- a fuse chip having a fuse unit including a plurality of fuse elements, electrical states of the fuse elements corresponding to a defective address of one of the defective memory cells, and having a redundancy cell control circuit controlling a redundancy cell operation of the defective memory cell based on the electrical state of the fuse elements.
The stacked memory according to claim 9, wherein the redundancy cell control circuit includes a circuit for outputting a signal obtained from a logical sum of a plurality of the control signals supplied to the plurality of areas.
A fuse chip comprising a fuse unit including a fuse unit including a plurality of fuse elements, electrical states of the fuse elements corresponding to a defective address of the defective memory cell, and having a redundancy cell control circuit controlling a redundancy cell operation of the defective memory cell based on the electrical state of the fuse elements.
Dependencies are inferred from the claim text.