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US 2009/0213128 A1Published application
System and method for instruction latency reduction in graphics processing
AssigneeQUALCOMM Incorporated
InventorLin Chen
Life of this patent
Estimating the term…
Abstract
A system, method and apparatus are disclosed, in which an instruction scheduler of a compiler, e.g., a shader compiler, reduces instruction latency based on a determined instruction distance between a dependent predecessor and successor instructions.
Claims50
A method comprising:
- identifying a dependence between two instructions in graphics processing instructions, one of the two instructions comprising a predecessor instruction and another of the two instructions comprising a successor instruction;
- determining an initial edge latency associated with the dependence between the predecessor and successor instructions;
- determining an instruction distance corresponding to the predecessor and successor instructions;
- and
- reducing the initial edge latency by the determined instruction distance to determine a reduced edge latency associated with the dependence between the predecessor and successor instructions.
2 more elements
An apparatus comprising:
- at least one programmable processing unit configured to implement at least a portion of a graphics pipeline;
- and
- an instruction scheduler configured to schedule instructions for execution by the at least one programmable processing unit using a reduced edge latency, said instruction scheduler configured to:
- identify a dependence between two instructions in graphics processing instructions, one of the two instructions comprising a predecessor instruction and another of the two instructions comprising a successor instruction;
- determine an initial edge latency associated with the dependence between the predecessor and successor instructions;
- determine an instruction distance corresponding to the predecessor and successor instructions;
- and
- reducing the initial edge latency by the determined instruction distance to determine a reduced edge latency associated with the dependence between the predecessor and successor instructions.
5 more elements
A computer-readable memory medium in which computer-executable program code is stored, the program code comprising code to:
- identify a dependence between two instructions in graphics processing instructions, one of the two instructions comprising a predecessor instruction and another of the two instructions comprising a successor instruction;
- determine an initial edge latency associated with the dependence between the predecessor and successor instructions;
- determine an instruction distance corresponding to the predecessor and successor instructions;
- and
- reduce the initial edge latency by the determined instruction distance to determine a reduced edge latency associated with the dependence between the predecessor and successor instructions.
2 more elements
An apparatus comprising:
- at least one programmable processing unit configured to implement at least a portion of a graphics pipeline;
- and
- an instruction scheduling means configured to schedule instructions for execution by said at least one programmable processing unit using a reduced edge latency, said instruction scheduling means comprising:
- means for identifying a dependence between two instructions in graphics processing instructions, one of the two instructions comprising a predecessor instruction and another of the two instructions comprising a successor instruction;
- means for determining an initial edge latency associated with the dependence between the predecessor and successor instructions;
- means for determining an instruction distance corresponding to the predecessor and successor instructions;
- and
- means for reducing the initial edge latency by the determined instruction distance to determine a reduced edge latency associated with the dependence between the predecessor and successor instructions.
5 more elements
Dependencies are inferred from the claim text.