Delay Circuit Having Long Delay Time and Semiconductor Device Comprising the Same
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-Hyung Kim, Min-Su Kim
Life of this patent
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Abstract
A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a second transistor connected to a ground voltage. The inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal. At least one capacitor unit is connected to an input terminal of the inverter such that a loading capacitance of the inverter circuit unit is increased.
Claims21
A delay circuit comprising:
- an inverter circuit unit having at least one inverter, each inverter comprising a first transistor connected to a supply voltage and a second transistor connected to a ground voltage, and
- at least one capacitor unit connected to the at least one inverter, the at least one capacitor unit providing a loading capacitance to the inverter circuit unit,
- wherein the inverter circuit unit in response to receiving an input signal outputs an output signal having a delay from the input signal, the delay corresponding to the loading capacitance.
A delay circuit comprising:
- an inverter circuit unit comprising at least one inverter stage, each inverter stage comprising:
- a pull-up transistor that switches a first voltage, and
- a pull-down transistor that switches a second voltage, the pull-down transistor being coupled in series to the pull-up transistor;
- and
- a resistance unit connected to at least one inverter stage and having a predetermined resistance independent of an input signal to the inverter circuit unit,
- wherein the inverter circuit unit, in response to receiving the input signal, outputs an output signal having a delay from the input signal, the delay corresponding to the predetermined resistance.
A method for delaying a signal, comprising:
- providing an inverter circuit unit having at least one inverter, each inverter comprising a first transistor connected to a supply voltage and a second transistor connected to a ground voltage,
- coupling:
- at least one capacitor unit to the at least one inverter, the at least one capacitor unit providing a loading capacitance to the inverter circuit unit, or
- a resistance unit to at least one inverter stage, the resistance unit having a predetermined resistance independent of an input signal to the inverter circuit,
- inputting an input signal to the inverter circuit;
- and
- outputting an output signal, the output signal:
- having a delay from the input signal, the delay corresponding to the loading capacitance if the at least one capacitor unit is coupled to the at least one inverter, or
- having a delay from the input signal, the delay corresponding to the predetermined resistance if the resistance unit is coupled to the at least one inverter stage.
A semiconductor device comprising a delay circuit which delays an input signal by a predetermined delay time and outputs the delayed signal,
- wherein the delay circuit comprises:
- an inverter circuit unit comprising one or more inverters, wherein each of the inverters comprises a first transistor connected to a supply voltage and a second transistor connected to a ground voltage, wherein the inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal;
- and
- at least one capacitor unit connected to the inverter circuit unit in order to increase loading capacitance of the inverter circuit unit.
Dependencies are inferred from the claim text.