Decoder circuit, decoding method, output circuit, electro-optical device, and electronic instrument

An output circuit comprising:

• a decoder circuit that decodes an (m+n)-bit address signal;
• and
• M (M is an integer) AND operation circuits,
• the decoder circuit including
• a first decoder section that decodes an m-bit address signal portion of the (m+n)-bit address signal, and
• a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal,
• the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and
• the signals from the first decoder section and the signals from the second decoder section being input to each of the M AND operation circuits.

A decoding method comprising.

• preparing an (m+n)-bit address signal;
• preparing an output enable signal that has a pulse width shorter than a logical time length of the (m+n)-bit address signal;
• decoding part of a lower-order n-bit address signal portion of the (m+n)-bit address signal to generate a first decoding result;
• decoding the remainder of the lower-order n-bit address signal portion and the output enable signal to generate a second decoding result;
• decoding the first decoding result and the second decoding result to generate a third decoding result;
• decoding a higher-order m-bit address signal portion of the (m+n)-bit address signal to generate a fourth decoding result;
• and
• decoding the third decoding result and the fourth decoding result to generate a fifth decoding result.