US 2009/0212818 A1 · Integrated circuit design method for improved testability

Abstract

An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a flipflop-replaced netlist from the netlist. In classifying the flipflops, a flipflop which is connected to an input terminal of the macro directly or through an input-side logic cone and operated on the same clock signal as the macro is classified as a control type, and a flipflop which has a data output connected to an input terminal of the macro directly or through the input-side logic cone and operated on a different clock signal is classified as a hold type. In the flipflop-replaced netlist, the flipflop classified as the control type is replaced with a control flipflop which is configurable to toggle a data output thereof in synchronization with the clock signal by configuring a control input separately provided a data input thereof, and the flipflop classified as the hold type is replaced with a first hold flipflop which is configurable to hold data so that the data hold therein is unchanged.

Claims13

Dependent claims

An integrated circuit design method comprising:

classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating said flipflops and said macro;
and
generating a flipflop-replaced netlist from said netlist,
wherein, in said classifying, a flipflop which is connected to an input terminal of said macro directly or through an input-side logic cone and operated on the same clock signal as said macro is classified as a control type, and a flipflop which has a data output connected to an input terminal of said macro directly or through said input-side logic cone and operated on a different clock signal is classified as a hold type,
wherein, in said flipflop-replaced netlist, said flipflop classified as said control type is replaced with a control flipflop which is configurable to toggle a data output thereof in synchronization with said clock signal by configuring a control input separately provided a data input thereof, and said flipflop classified as said hold type is replaced with a first hold flipflop which is configurable to hold data so that said data held therein is unchanged.

2 more elements

A semiconductor integrated circuit comprising:

a macro;
at least one control flipflop having a data output connected to an input terminal of said macro directly or through an input-side logic cone and operating on the same clock signal as said macro;
and
a first hold flipflop having a data output connected to an input terminal of said macro directly or through an input-side logic cone and operating on a different clock signal,
wherein said control flipflop is configurable to toggle a data output thereof in synchronization with said clock signal by configuring at least one control input separately provided a data input thereof, and
wherein said first hold flipflop is configurable to hold data so that said data held therein is unchanged.

3 more elements

Dependencies are inferred from the claim text.

Integrated circuit design method for improved testability

Life of this patent

Integrated circuit design method for improved testability

Life of this patent

Abstract

Claims13