Structures for testing and locating defects in integrated circuits

A method for detecting defects during semiconductor device processing, comprising:

• providing a substrate having a semiconductor comprising layer formed thereon, wherein an application circuit and one or more test circuits are formed in or on the layer, wherein the test circuits and the application circuit are electrically isolated from each other, and wherein each of the test circuits comprises:
• a plurality of semiconductor devices connected in parallel;
• a first contact pad coupled to a first terminal of the semiconductor devices, and
• at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices;
• directing an electron current inducing beam to the test circuit;
• measuring a current between the first and the second contact pads in the test circuit;
• determining an electron beam induced current (EBIC);
• and
• identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC.