Supply current based testing of CMOS output stages
AssigneeDialog Semiconductor GmbH
InventorsHans Martin von Staudt, Alan Somerville
Life of this patent
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Abstract
A CMOS driver test configuration, which allows both leakage current and load current testing, using a single monitor, or current meter, located in a power lead of a tester connected to a power pad servicing the driver circuits. Both leakage testing and load current testing for CMOS drivers is described. The test configuration allows a plurality of driver circuits connected in parallel between power pads to be tested simultaneously. An ESD device, internal to the chip, is used as a load during load current testing in chip testing, and an external load is used during package testing in order to include the bonding means between the chip output pad of the driver and the package I/O pin in the current path during load current testing.
Claims17
A method of current testing semiconductor drivers;
- comprising:
- a) forming driver circuits on a semiconductor device, comprising CMOS circuits, by connecting an NMOS transistor in series with a PMOS transistor between a first and a second power supply pad of said semiconductor device;
- b) connecting a tester to said semiconductor device, whereby a first power supply lead of said tester connected to the first power pad and a second power supply lead of said tester connected to the second power pad, wherein current flow to said driver circuits measured by a current monitor located in said first power supply lead
- c) selecting the NMOS transistor, selecting a first load device paralleling said PMOS transistor and measuring current flow through said NMOS transistor with said current monitor;
- and
- d) selecting the PMOS transistor, selecting a second load device paralleling said NMOS transistor and measuring current flow through said PMOS transistor with said current monitor.
A circuit to test current of CMOS driver circuits, comprising:
- a) a CMOS driver circuit comprising a PMOS transistor connected to an NMOS transistor to form an output and further said CMOS driver circuit connected between a first and second power pad of an integrated circuit chip;
- b) a first ESD (electrostatic discharge) device select-ably connected between a source and drain of the PMOS transistor;
- c) a second ESD device select-ably connected between the source and drain of the NMOS transistor;
- d) a first tester lead of a tester connected to the first power pad and further comprising a current monitor circuit to measure current;
- e) a second tester lead of said tester connected to the second power pad;
- f) said NMOS transistor and said first ESD device selected to measure current through the NMOS device using said current monitor circuit;
- and
- g) said PMOS transistor and said second ESD device selected to measure current through the PMOS transistor using said current monitor circuit.
A CMOS driver current measurement circuit, comprising:
- a) means for forming on an integrated circuit chip a CMOS driver between first and second power pads, wherein the CMOS driver further comprises an NMOS transistor, a PMOS transistor and a driver output;
- b) a means for powering said CMOS driver from a tester through the first and second power pads;
- c) a means for said tester to measure current flowing from the tester to said CMOS driver;
- d) a means for selecting the PMOS transistor and a first load device to allow current to flow through the PMOS transistor;
- and
- e) a means to selecting the NMOS transistor and a second load device to allow current to flow through the NMOS transistor.
Dependencies are inferred from the claim text.