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US 2009/0212416 A1Published application
Integrated circuit package and method of manufacturing same
AssigneeIntel Corporation
InventorOswald L. Skeete
Life of this patent
Estimating the term…
Abstract
An integrated circuit package includes a substrate (110, 210) having a first surface (111, 211) and an opposing second surface (112, 212), and a die platform (130, 230) adjacent to the first surface of the substrate. The substrate has a recess (120, 220) therein. The integrated circuit package further includes a capacitor (140, 240) in the recess of the substrate.
Claims20
An integrated circuit package comprising:
- a substrate having a first surface and an opposing second surface, the substrate containing a recess therein;
- a die platform adjacent to the first surface of the substrate;
- and
- a capacitor in the recess of the substrate.
1 more element
An integrated circuit package comprising:
- a substrate having a first surface and an opposing second surface, the substrate containing a recess therein;
- a bumpless build-up layer component physically and electrically coupled to the first surface of the substrate, the bumpless build-up layer component comprising:
- a die;
- a plurality of build-up layers adjacent to the die;
- and
- a bumpless build-up layer grid array adjacent to the build-up layers;
- and
- a plurality of capacitors in the recess of the substrate.
5 more elements
A method of manufacturing an integrated circuit package, the method comprising:
- providing a substrate having a first surface and an opposing second surface, the substrate containing a recess therein;
- attaching a die platform to the first surface of the substrate;
- and
- placing a capacitor in the recess of the substrate.
1 more element
Dependencies are inferred from the claim text.