Semiconductor package accomplishing fan-out structure through wire bonding

A semiconductor package comprising:

• a first semiconductor chip including a plurality of first solder ball pads and a plurality of first bond fingers formed on a first surface;
• a first multi-layered printed circuit board including:
• a plurality of second bond fingers and a plurality of second solder ball pads formed on a first surface,
• a chip recess configured to receive the semiconductor chip, and
• a plurality of third solder ball pads formed on a second surface,
• wherein the plurality of second bond fingers and the plurality of second solder ball pads are distributed about portions of the periphery of the chip recess,
• wherein the plurality of first bond pads and the plurality of second bond pads correspond in position to one another when the semiconductor chip is located in the chip recess;
• a plurality of wires to connect the first bond fingers and the second bond fingers;
• an encapsulant to seal the plurality of wires;
• and
• a first plurality of solder balls attached to the first plurality of solder ball pads and to the plurality of second solder ball pads.