Stackable Semiconductor Package and Stack Method Thereof

A stackable semiconductor package comprising:

• a first semiconductor package including a first substrate, at least one first semiconductor die mounted on the first substrate to be electrically connected to the first substrate, and a first encapsulant molded on the first substrate to surround the first semiconductor die;
• a second semiconductor package including a second substrate, at least one second semiconductor die mounted on the second substrate to be electrically connected to the second substrate, and a second encapsulant molded on the second substrate to surround the second semiconductor die;
• and
• one or more interposers positioned between the first and second semiconductor packages to electrically connect the first substrate to the second substrate so that the first and second semiconductor packages are stacked in the vertical direction.

A stack method of a stackable semiconductor package, the method comprising the steps of:

• mounting at least one first semiconductor die on a first substrate to electrically connect the first substrate to the first semiconductor die, and encapsulating the first semiconductor die with a first encapsulant to prepare a first semiconductor package;
• mounting at least one second semiconductor die on a second substrate to electrically connect the second substrate to the second semiconductor die, and encapsulating the second semiconductor die with a second encapsulant to prepare a second semiconductor package;
• preparing one or more interposers, each of which includes an insulating layer, lower conductive pads and lower solder balls sequentially formed on the lower surface of the insulating layer, and upper conductive pads and upper solder balls sequentially formed on the upper surface of the insulating layer;
• positioning and aligning the interposers between the first and second substrates such that the lower solder balls come into contact with the first substrate and the upper solder balls come into contact with the second substrate;
• placing the first semiconductor package, the second semiconductor package and the interposers in a furnace at a temperature of 180 to 300° C. to melt the upper and lower solder balls so that the lower solder balls are electrically connected to the first substrate and the upper solder balls are electrically connected to the second substrate (reflow);
• and
• cooling the first semiconductor package, the second semiconductor package and the interposers to room temperature to cure the upper and lower solder balls.