Semiconductor transistors having high-k gate dielectric layers and metal gate electrodes

A semiconductor structure fabrication method, comprising:

• providing a semiconductor structure which includes (i) a semiconductor substrate which includes a channel region, (ii) a first source/drain region on the semiconductor substrate, (iii) a second source/drain region on the semiconductor substrate, wherein the channel region is disposed between the first and second source/drain regions, and (iv) a first gate dielectric corner region, wherein the first gate dielectric corner region is in direct physical contact with the channel region;
• forming a final gate dielectric region on the semiconductor substrate,
• wherein the final gate dielectric region comprises a first dielectric material,
• wherein the final gate dielectric region is in direct physical contact with the channel region via an interfacing surface, and
• wherein the interfacing surface defines a reference direction perpendicular to the interfacing surface and pointing from the final gate dielectric region toward the channel region;
• and
• forming a final gate electrode region on the final gate dielectric region,
• wherein the final gate electrode region comprises an electrically conductive material,
• wherein the final gate dielectric region is disposed between and in direct physical contact with the channel region and the final gate electrode region,
• wherein the first gate dielectric corner region comprises a second dielectric material that is different from the first dielectric material,
• wherein the first gate dielectric corner region is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region,
• wherein the first gate dielectric corner region is not in direct physical contact with the final gate electrode region, and
• wherein the first gate dielectric corner region overlaps the final gate electrode region in the reference direction.