Semiconductor device and method of fabricating the same
AssigneeKabushiki Kaisha Toshiba
InventorHiroyuki YAMASAKI
Life of this patent
Estimating the term…
Abstract
A semiconductor device according to one embodiment includes: a semiconductor substrate comprising an element isolation region; two gate electrodes formed in substantially parallel on the semiconductor substrate via respective gate insulating films; two channel regions each formed in regions of the semiconductor substrate under the two gate electrodes; a source/drain region formed in a region of the semiconductor substrate sandwiching the two channel regions; a first stress film formed so as to cover the semiconductor substrate and the two gate electrodes; and a second stress film formed in at least a portion of a void, the void being formed in a region between the two gate electrodes.
Claims20
A semiconductor device, comprising:
- a semiconductor substrate comprising an element isolation region;
- two gate electrodes formed in substantially parallel on the semiconductor substrate via respective gate insulating films;
- two channel regions each formed in regions of the semiconductor substrate under the two gate electrodes;
- a source/drain region formed in a region of the semiconductor substrate sandwiching the two channel regions;
- a first stress film formed so as to cover the semiconductor substrate and the two gate electrodes;
- and
- a second stress film formed in at least a portion of a void, the void being formed in a region between the two gate electrodes.
A method of fabricating a semiconductor device, comprising:
- forming two gate electrodes in substantially parallel on a semiconductor substrate via respective gate insulating films;
- forming a source/drain region in the semiconductor substrate on both sides of the two gate electrodes;
- forming a first stress film on the semiconductor substrate and the two gate electrodes;
- forming an interlayer insulating film on the first stress film;
- forming a contact hole in the first stress film and the interlayer insulating film on the source/drain region so as to penetrate through a void, the void being in the first stress film or the interlayer insulating film in a region between the two gate electrodes;
- and
- forming a second stress film in at least a portion of the void via the contact hole.
Dependencies are inferred from the claim text.