Gate Effective-Workfunction Modification for CMOS

A CMOS circuit, comprising:

• a PFET device, said PFET device comprises a PFET channel hosted in a Si based material, and a PFET gate stack overlapping said PFET channel, wherein said PFET gate stack comprises a first gate layer of a gate metal material, said PFET device further comprises a PFET gate insulator in-between said PFET gate stack and said PFET channel, wherein said PFET gate insulator comprises at least two layers:
• a first HfO2 layer and an aluminum oxide layer, wherein said first HfO2 layer and said aluminum oxide layer are in direct physical contact with each other, and said aluminum oxide layer is between about 0.1 nm and about 1 nm thick;
• and
• an NFET device, said NFET device comprises an NFET channel hosted in said Si based material, and an NFET gate stack overlapping said NFET channel, wherein said NFET gate stack comprises a second gate layer of said gate metal material, said NFET device further comprises an NFET gate insulator in-between said NFET gate stack and said NFET channel, wherein said NFET gate insulator comprises a second HfO2 layer.

A method for fabricating a CMOS circuit, comprising:

• using first type and second type devices, wherein said first type and second type devices are both characterized as being metal gate devices with high-k gate insulators;
• blanket disposing over said first type and second type devices a high-k insulator material;
• blanket disposing over said high-k insulator material a gate metal material;
• concomitantly patterning a first gate layer and a second gate layer and a first gate dielectric layer a second gate dielectric layer out of said gate metal material and said high-k insulator material;
• in said first type device, forming a first interfacial control layer in such manner to have said first gate dielectric layer in-between and in direct contact with said first interfacial control layer and said first gate layer;
• in said second type device, forming a second interfacial control layer in such manner to have said second interfacial control layer in-between and in direct contact with said second gate dielectric layer and said second gate layer;
• and
• selecting differing materials for forming said first interfacial control layer and for forming said second interfacial control layer.

A method for fabricating a CMOS circuit, comprising:

• using NFET and PFET devices, wherein said NFET and PFET devices are both characterized as being metal gate devices with high-k gate insulators;
• blanket disposing over said NFET and PFET devices a high-k insulator material;
• blanket disposing over said high-k insulator material a gate metal material;
• concomitantly patterning an NFET gate layer and a PFET gate layer and an NFET gate dielectric layer and a PFET gate dielectric layer out of said gate metal material and said high-k insulator material;
• and
• in said PFET device, forming an aluminum oxide layer in such manner as to have said PFET gate dielectric layer in direct contact with said aluminum oxide layer, and selecting said aluminum oxide layer to be between about 0.1 nm and about 1 nm thick.