Semiconductor device and a method of manufacturing the same

A semiconductor device including a trench gate type MISFET, comprising:

• a semiconductor substrate having a main surface and a bottom surface opposite to the main surface, the semiconductor substrate being a first conductivity type;
• a first semiconductor layer formed on the main surface of the semiconductor substrate, the first semiconductor layer having a top surface apart from the semiconductor substrate, the first semiconductor layer being the first conductivity type, and the first semiconductor layer acting as a drain region of the MISFET;
• a trench formed on the top surface of the first semiconductor layer, a distance between the top surface of the first semiconductor layer and a bottom of the trench being not more than 1 μm;
• a gate insulating film of the MISFET formed on an inner surface of the trench;
• a gate electrode of the MISFET formed on the gate insulating film in the trench;
• and
• a channel forming region of the MISFET formed in the first semiconductor layer;
• the channel forming region being in contact with the trench, the bottom of the trench being positioned below a bottom of the channel forming region, and the channel forming region being a second conductivity type opposite to the first conductivity type,
• wherein the channel forming region is formed by a first ion implantation;
• a source region of the MISFET is formed over the channel forming region in the first semiconductor layer, the source region is in contact with the trench, and the source region is the first conductivity type;
• and
• a punch through stopper region is formed between the source region and the channel forming region in the first semiconductor layer, the punch through stopper region is the second conductivity type, and the punch through stopper region has a higher impurity concentration than the channel forming region,
• wherein the punch through stopper region is formed by a second ion implantation different from the first ion implantation such that a concentration distribution of the punch through stopper region is decided by a concentration distribution of the second ion implantation.

A semiconductor device including a trench gate type MISFET, comprising:

• a semiconductor substrate having a main surface and a bottom surface opposite to the main surface, the semiconductor substrate being a first conductivity type;
• a first semiconductor layer formed on the main surface of the semiconductor substrate, the first semiconductor layer having a top surface apart from the semiconductor substrate, the first semiconductor layer being the first conductivity type, and the first semiconductor layer acting as a drain region of the MISFET;
• a trench formed on the top surface of the first semiconductor layer, a distance between the top surface of the first semiconductor layer and a bottom of the trench being not more than 1 μm;
• a gate insulating film of the MISFET formed on an inner surface of the trench;
• a gate electrode of the MISFET formed on the gate insulating film in the trench;
• a channel forming region of the MISFET formed in the first semiconductor layer, the channel forming region being in contact with the trench, the bottom of the trench being positioned below a bottom of the channel forming region, and the channel forming region being a second conductivity type opposite to the first conductivity type,
• wherein the channel forming region is formed by a first ion implantation and by a diffusion of the first ion using heat treatment;
• a source region of the MISFET formed over the channel forming region in the first semiconductor layer, the source region being in contact with the trench, and the source region being the first conductivity type;
• and
• a punch through stopper region formed between the source region and the channel forming region in the first semiconductor layer, the punch through stopper region being the second conductivity type, and the punch through stopper region having a higher impurity concentration than the channel forming region,
• wherein the punch through stopper region is formed by a second ion implantation different from the first ion implantation such that a formation position of the punch through stopper region and a concentration distribution of the punch through stopper region are decided by an implantation energy of the second ion implantation.

A method of manufacturing a semiconductor device including a trench gate type MISFET, the trench gate type MISFET comprising:

• a semiconductor substrate having a main surface and a bottom surface opposite to the main surface, the semiconductor substrate having a first conductivity type;
• a first semiconductor layer formed on the main surface of the semiconductor substrate, the first semiconductor layer having a top surface apart from the semiconductor substrate, the first semiconductor layer having the first conductivity type, and the first semiconductor layer acting as a drain region of the MISFET;
• a trench formed on the top surface of the first semiconductor layer, a distance between the top surface of the first semiconductor layer and a bottom of the trench being not more than 1 mm;
• a gate insulating film of the MISFET formed on an inner surface of the trench;
• a gate electrode of the MISFET formed on the gate insulating film in the trench;
• a channel forming region of the MISFET formed in the first semiconductor layer, the channel forming region being in contact with the trench, the bottom of the trench being positioned below a bottom of the channel forming region, and the channel forming region having a second conductivity type opposite to the first conductivity type;
• a source region of the MISFET formed over the channel forming region in the first semiconductor layer;
• the source region being in contact with the trench, and the source region having the first conductivity type;
• and
• a punch through stopper region formed between the source region and channel forming region in the first semiconductor layer, the punch through stopper region having the second conductivity type, and the punch through stopper region having a higher impurity concentration than the channel forming region,
• wherein the method comprising steps of:
• introducing a first impurity and forming the channel forming region by a first ion implantation;
• and
• introducing a second impurity and forming the punch through stopper region by a second ion implantation different from the first ion implantation thereby deciding a concentration distribution of the punch through stopper region by a concentration distribution of the second ion implantation.

A method of manufacturing a semiconductor device including a trench gate type MISFET, the trench gate type MISFET comprising:

• a semiconductor substrate having a main surface and a bottom surface opposite to the main surface, the semiconductor substrate having a first conductivity type;
• a first semiconductor layer formed on the main surface of the semiconductor substrate, the first semiconductor layer having a top surface apart from the semiconductor substrate, the first semiconductor layer having the first conductivity type, and the first semiconductor layer acting as a drain region of the MISFET;
• a trench formed on the top surface of the first semiconductor layer, a distance between the top surface of the first semiconductor layer and a bottom of the trench being not more than 1 mm;
• a gate insulating film of the MISFET formed on an inner surface of the trench;
• a gate electrode of the MISFET formed on the gate insulating film in the trench;
• a channel forming region of the MISFET formed in the first semiconductor layer, the channel forming region being in contact with the trench, the bottom of the trench being positioned below a bottom of the channel forming region, and the channel forming region having a second conductivity type opposite to the first conductivity type,
• wherein the channel forming region is formed by a first ion implantation and by a diffusion of the first ion using a heat treatment;
• a source region of the MISFET formed over the channel forming region in the first semiconductor layer;
• the source region being in contact with the trench, and the source region having the first conductivity type;
• and
• a punch through stopper region formed between the source region and channel forming region in the first semiconductor layer, the punch through stopper region having the second conductivity type, and the punch through stopper region having a higher impurity concentration than the channel forming region,
• wherein the punch through stopper region is formed by a second ion implantation different from the first ion implantation such that a formation position of the punch through stopper region and a concentration distribution of the punch through stopper region are decided by an implantation energy of the second ion implantation,
• wherein the method comprising steps of:
• forming the channel forming region by a first ion implantation and by a diffusion of the first ion using a heat treatment;
• and
• forming the punch through stopper region by a second ion implantation different from the first ion implantation thereby deciding a formation position of the punch through stopper region and a concentration distribution of the punch through stopper region by an implantation energy of the second ion implantation.