Non-volatile two-transistor programmable logic cell and array layout

An array of non-volatile memory cells including:

• a semiconductor body;
• a first plurality of memory-transistor wells disposed within the semiconductor body;
• a first plurality of switch-transistor wells disposed within the semiconductor body to a first side of the first plurality of memory-transistor wells and electrically isolated from memory-transistor wells;
• a first plurality of memory-transistors formed within the first plurality of memory-transistor wells, each including spaced-apart source and drain regions;
• a first plurality of switch-transistors formed within the first plurality of switch-transistor wells, each associated with one of the first plurality of memory-transistors and including spaced-apart source and drain regions;
• a second plurality of switch-transistors formed within the first plurality of switch-transistor wells, each associated with one of the first plurality of memory-transistors and formed in a same switch-transistor well as one of the first plurality of switch-transistors associated with that associated one of the first plurality of memory-transistors, and including spaced-apart source and drain regions;
• a floating gate associated with each memory-transistor, each floating gate insulated from and self-aligned with the source and drain regions of the memory-transistor and each switch-transistor with which it is associated;
• and
• a control gate associated with each memory-transistor, each control gate disposed above and self aligned with the floating gate associated with that associated memory-transistor and with the source and drain regions of that associated memory-transistor and each switch-transistor with which it is associated.