Field effect transistor with reduced overlap capacitance

A metal-oxide-semiconductor field effect transistor (MOSFET) structure comprising:

• a gate dielectric abutting and overlying a body portion, a source extension region, and a drain extension region in a semiconductor substrate;
• a metal gate portion vertically abutting said gate dielectric portion;
• a dielectric liner vertically abutting said source extension region or said drain extension region and laterally abutting said gate dielectric and said metal gate portion;
• and
• an inner gate spacer overlying an entire periphery of said metal gate portion.

A metal-oxide-semiconductor field effect transistor (MOSFET) structure comprising:

• a gate dielectric abutting and overlying a body portion, a source extension region, and a drain extension region in a semiconductor substrate;
• a metal gate portion vertically abutting said gate dielectric portion;
• a gate spacer vertically abutting said source extension region or said drain extension region and laterally abutting said gate dielectric and said metal gate portion;
• and
• an inner gate spacer overlying an entire periphery of said metal gate portion.

A method of forming a semiconductor structure comprising:

• forming a stack of a gate dielectric, a metal gate portion, and one of a gate conductor and a disposable gate portion on a semiconductor substrate, wherein sidewalls of said gate dielectric, said metal gate portion, and one of said gate conductor and said disposable gate portion are substantially vertically coincident;
• laterally recessing a sidewall of said metal gate portion relative to a sidewall of said one of said gate conductor and said disposable gate portion;
• forming a source extension region and a drain extension region underlying said metal gate portion;
• and
• forming a gate spacer on said gate dielectric, said one of said gate conductor and said disposable gate portion, said source extension region, and said drain extension region.