Method of fabricating a buried-gate semiconductor device and corresponding integrated circuit
AssigneesSTMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
InventorsEmilie Bernard, Bernard Guillaumot, Philippe Coronel
Life of this patent
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Abstract
A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device.
Claims19
A method of fabricating a semiconductor transistor device comprising a semiconductive channel region and a gate region, the gate region comprising at least one buried part extending under the semiconductive channel region, wherein fabricating comprises forming the buried part of the gate region by:
- forming a cavity under the semiconductive channel region,
- at least partial filling the cavity with at least silicon and a metal, and
- forming a silicide of said metal in the cavity.
A method of fabricating a semiconductor transistor device comprising a semiconductive channel region and a gate region, the gate region comprising at least one buried part extending under the semiconductive channel region, wherein fabricating comprises forming the gate region by:
- forming, on a top surface of a substrate, a stack comprising at least one layer of silicon placed above a sacrificial layer formed from a material that is selectively eliminable relative to the silicon,
- epitaxially growing silicon on lateral walls of the stack,
- anisotropically etching the stack so as to etch a part of the epitaxially grown silicon and access at least one of the ends of the sacrificial layer,
- selective isotropic etching of the sacrificial layer,
- forming, on walls of the cavity resulting from the selective isotropic etching, a layer comprising a dielectric material,
- conformally depositing, in the cavity, a layer comprising silicon,
- conformally depositing, in the cavity, a layer comprising metal, and
- annealing to form a silicide of said metal in the cavity, the silicide being the at least one buried part of the gate region.
A semiconductor transistor device comprising a semiconductive channel region and a gate region, the gate region comprising at least one buried part extending under the channel region, wherein the buried part of the gate region comprises a metal silicide.
A method of fabricating a semiconductor transistor device comprising a semiconductive channel region and a gate region, the gate region comprising at least one buried part extending under the semiconductive channel region, wherein fabricating comprises:
- forming a stack comprising a layer of silicon above a sacrificial layer,
- forming source/drain regions on either end of the stack, selectively etching away the sacrificial layer from either side of the stack to form a cavity,
- conformally depositing a layer of silicon and a layer of metal in the cavity, and
- annealing to form a silicide of said metal in the cavity, the silicide being the at least one buried part of the gate region.
Dependencies are inferred from the claim text.