Hetero Field Effect Transistor and Manufacturing Method Thereof

A method of manufacturing a hetero field effect transistor that comprises a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer to allow a generation of a two dimensional carrier gas layer of a first conductive type on a heterojunction interface between the first semiconductor layer and the second semiconductor layer, a third semiconductor layer formed on the second semiconductor layer and having an impurity introduced therein, a source electrode formed on the third semiconductor layer, a drain electrode formed on the third semiconductor layer and separated from the source electrode, a fourth semiconductor layer formed on or above the second semiconductor layer and has a second conductive type which is different from the first conductive type, and a gate electrode electrically connected on the fourth semiconductor layer, wherein the fourth semiconductor layer is located adjacent to and surrounded by the third semiconductor layer, said method comprising:

• forming the third semiconductor layer having an impurity of the second conductive type introduced therein;
• and
• selectively activating the impurity of the third semiconductor layer to form the fourth semiconductor layer.