Hetero Field Effect Transistor and Manufacturing Method Thereof

A hetero field effect transistor comprising:

• a main semiconductor region comprising a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to allow a generation of a two-dimensional carrier gas layer of a first conductive type on a heterojunction interface between the first semiconductor layer and the second semiconductor layer;
• a source electrode formed on the main semiconductor region;
• a drain electrode formed on the main semiconductor region and separated from the source electrode;
• a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on a second semiconductor layer and located between the source electrode and the drain electrode;
• a gate electrode formed on the third semiconductor layer;
• and
• a diffusion layer of the second conductive type formed on the second semiconductor layer at a region immediately below the gate electrode.

A method of manufacturing a hetero field effect transistor that comprises:

• a main semiconductor region comprising a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to allow a generation of a two-dimensional carrier gas layer on a heterojunction interface between the first semiconductor layer and the second semiconductor layer;
• a source electrode formed on the main semiconductor region;
• a drain electrode formed on the main semiconductor region and separated from the source electrode;
• a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on the second semiconductor layer and located between the source electrode;
• and a gate electrode formed on the third semiconductor layer;
• wherein a concave portion is formed in an upper surface of the second semiconductor layer at a region immediately below the gate electrode, said method comprising:
• etching the second semiconductor layer to form the concave portion in the upper surface of the second semiconductor layer, and
• thereafter forming the third semiconductor layer.

A method of manufacturing a hetero field effect transistor that comprises:

• a main semiconductor region comprising a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to allow a generation of a two-dimensional carrier gas layer on a heterojunction interface between the first semiconductor layer and the second semiconductor layer;
• a source electrode formed on the main semiconductor region;
• a drain electrode formed on the main semiconductor region and separated from the source electrode;
• a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on a second semiconductor layer and located between the source electrode and the drain electrode;
• a gate electrode formed on the third semiconductor layer;
• and a diffusion layer of the second conductive type formed on the second semiconductor layer at a region immediately below the gate electrode, said method comprising:
• forming the third semiconductor layer on the second semiconductor layer by a crystal growth, and
• thereafter diffusing an impurity of the second conductive type into the third semiconductor layer to form the diffusion layer.