Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate;
• a thin film transistor (TFT) formed on the substrate and having a source electrode and a drain electrode;
• a passivation layer and a planarization layer formed on the TFT;
• and
• a via hole penetrating the passivation layer and the planarization layer and exposing a portion of either the source electrode and or the drain electrode, and having a triple profile in which an upper portion of the via hole has a wet etch profile, a middle portion of the via hole has a high selectivity dry etch profile and a lower portion of the via hole has a high etch rate dry etch profile.

A semiconductor device, comprising:

• a substrate;
• a metal interconnection line formed on the substrate;
• an interlayer dielectric formed on the metal interconnection line;
• and
• a via hole penetrating the interlayer dielectric and exposing a portion of the metal interconnection line, and having a triple profile in which an upper portion of the via hole has a wet etch profile, a middle portion of the via hole has a high selectivity dry etch profile and a lower portion of the via hole has a high etch rate dry etch profile.

A semiconductor device, comprising:

• a substrate;
• a semiconductor layer, a gate insulating layer, and a gate electrode formed on the substrate;
• a planarization layer formed on the substrate;
• and
• a via contact hole penetrating the planarization layer and the gate insulating layer and exposing a portion of the semiconductor layer, and having a triple profile in which an upper portion of the via contact hole has a wet etch profile, a middle portion of the via contact hole has a high selectivity dry etch profile and a lower portion of the via contact hole has a high etch rate dry etch profile.

A semiconductor device, comprising:

• a substrate;
• a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric formed on the substrate;
• a thin film transistor (TFT) region including a contact hole, the contact hole penetrating the gate insulating layer and the interlayer dielectric, exposing a portion of the semiconductor layer, and having a triple profile in which an upper portion of the contact hole has a wet etch profile, a middle portion of the contact hole has a high selectivity dry etch profile and a lower portion of the contact hole has a high etch rate dry etch profile;
• a metal interconnection line and an insulating layer formed on the substrate and spaced apart from the TFT region by a predetermined interval;
• and
• a via hole penetrating the insulating layer and having a triple profile in which an upper portion of the via hole has a wet etch profile, a middle portion of the via hole has a high selectivity dry etch profile and a lower portion of the via hole has a high etch rate dry etch profile.