Semiconductor device and manufacturing method thereof
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorShunpei YAMAZAKI
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Abstract
A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217-220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFT of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.
Claims12
A semiconductor device comprising:
- a driver circuit including a first n-channel TFT and a p-channel TFT, and a pixel portion including a second n-channel TFT;
- the first n-channel TFT including a first semiconductor layer, a gate insulating film over the first semiconductor layer, and a first gate electrode over the gate insulating film, wherein the first semiconductor layer contains a first channel forming region, a pair of first impurity regions, a pair of second impurity regions, and a pair of third impurity regions;
- the p-channel TFT including a second semiconductor layer, the gate insulating film over the second semiconductor layer, and a second gate electrode over the gate insulating film, wherein the second semiconductor layer contains a second channel forming region, and a pair of fourth impurity regions;
- the second n-channel TFT including a third semiconductor layer, the gate insulating film over the third semiconductor layer, and a third gate electrode over the gate insulating film, wherein the third semiconductor layer contains a third channel forming region, a pair of fifth impurity regions, and a pair of sixth impurity regions,
- wherein each of the first gate electrode, the second gate electrode, and the third gate electrode has a tapered side surface,
- wherein the pair of first impurity regions are overlapped with the tapered side surface of the first gate electrode,
- wherein the pair of second impurity regions are not overlapped with the first gate electrode,
- wherein the pair of fifth impurity regions are not overlapped with the third gate electrode,
- wherein the pair of third impurity regions contain an impurity imparting n-type at a higher concentration than that of the pair of first impurity regions and the pair of second impurity regions, and
- wherein the pair of sixth impurity regions contain an impurity imparting n-type at a higher concentration than that of the pair of fifth impurity regions.
Dependencies are inferred from the claim text.