Display panel and method for manufacturing the same

A display panel comprising:

• a lower gate line including a gate electrode;
• a gate insulating layer disposed on the lower gate line;
• a semiconductor disposed on the gate insulating layer;
• a lower data line including a source electrode disposed overlapping a portion of the semiconductor;
• a drain electrode disposed substantially opposite to the source electrode and overlapping a portion of the semiconductor;
• an insulating layer disposed on the lower data line and the drain electrode and including a plurality of trenches exposing the lower gate line and the data line;
• an upper gate line disposed in the trench on the lower gate line;
• an upper data line disposed in the trench on the lower data line;
• and
• a pixel electrode connected to the drain electrode.

A method for manufacturing a display panel comprising:

• forming a lower gate line;
• disposing a semiconductor on the lower gate line;
• disposing a lower data line substantially perpendicular to the lower gate line;
• disposing an insulating layer having a plurality of trenches exposing the lower gate line and the lower data line on the lower data line;
• disposing an upper gate line on the lower gate line and within the plurality of trenches;
• and
• disposing an upper data line on the lower data line and within the plurality of trenches.

A method for manufacturing a display panel comprising:

• forming a lower gate line including a gate electrode;
• disposing a gate insulating layer on the lower gate line;
• disposing a semiconductor overlapping the gate electrode on the gate insulating layer;
• disposing a lower data line on the gate insulating layer, the lower data line including a source electrode overlapping a portion of the semiconductor;
• disposing a drain electrode overlapping a portion of the semiconductor and substantially opposite to the source electrode;
• disposing an insulating layer on the lower data line and the drain electrode;
• removing a portion of the insulating layer and the gate insulating layer to form a plurality of trenches exposing the lower gate line and the lower data line;
• disposing an upper gate line on the lower gate line within the plurality of trenches;
• disposing an upper data line on the lower data line within the plurality of trenches;
• and
• connecting a pixel electrode to the drain electrode.