Delay stabilization for skew tolerance
AssigneeFairchild Semiconductor Corporation
InventorDavid P. Morrill
Life of this patent
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Abstract
In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC.
Claims14
An integrated circuit containing at least two separate timing circuits, wherein a time specification for at least first timing circuit is known, the integrated circuit comprising:
- a first variable control circuit that controls the timing of at least a first timing circuit;
- a driver that outputs a control signal to the first variable control circuit in response to a trim value, wherein when the at least first timing circuit does not meet its time specification, the trim value is determined and applied to the driver so that the at least first timing circuit meets its timing specification, and
- a second variable control circuit that controls the timing of a second timing circuit, wherein the driver outputs a second control signal to the second variable control circuit to change the timing of the second timing circuit.
The serializer/deserializer of claim 14 wherein the driver comprises transistor switches that connect resistors to a power supply and to ground, the resistors and transistor switches forming a resistor divider wherein the resistor divider outputs the variable control signal, wherein a trim value, when applied to the driver, selectively activates the transistor switches to change the output of the resistor divider and thus the variable control signal.
A method for trimming an integrated circuit containing at least two separate timing circuits, wherein a time specification for at least a first timing circuit is known, the method comprising the steps of:
- measuring the timing of at least first timing circuit;
- wherein when the at least first timing circuit does not meet its time specification;
- determining a trim value;
- changing the timing of the at least one timing circuit to meet its time specification by applying the trim value to a first variable control circuit that controls the timing of the at least first timing circuit, and
- changing the timing of a second timing circuit by applying the trim value to a second variable control circuit that controls the timing of the second timing circuit.
Dependencies are inferred from the claim text.