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US 2009/0168519 A1Published application
Architecture of a nvDRAM array and its sense regime
AssigneeSimtek
InventorsAndreas Scade, Stefan Guenther
Life of this patent
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Abstract
A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.
Claims11
A memory system comprising:
- a plurality of nvDRAM cells;
- a plurality of sense amplifiers;
- and
- the nvDRAM cells comprising a single data interface, the single data interface coupling the nvDRAM cells to the sense amplifiers, the single data interface operating only at DRAM levels for both volatile and nonvolatile memory operations involving the nvDRAM cells.
1 more element
A device comprising:
- at least one processor;
- and
- a memory system comprising a plurality of nvDRAM cells and a plurality of sense amplifiers, the nvDRAM cells comprising a single data interface, the single data interface coupling the nvDRAM cells to the sense amplifiers, the single data interface operating only at DRAM levels for both volatile and nonvolatile memory operations involving the nvDRAM cells.
A process of operating a memory array comprising:
- performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.
Dependencies are inferred from the claim text.