High-speed amplitude detector with a digital output
AssigneeIntel Corporation
InventorSami Hyvonen
Life of this patent
Estimating the term…
Abstract
An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described.
Claims15
An electrical circuit, comprising:
- a first FET that partially controls output voltage signals responsive to an input voltage;
- a gate load coupled to a gate of the first FET;
- a drain load coupled to a drain of the first FET;
- a source load coupled to a source of the first FET;
- a controllable variable current generator providing a current to the source of the first FET, biasing the source of the first FET to a reference voltage;
- and
- a first input conductor coupled to the gate of the first FET and an input voltage signal including a variable input signal applied to the first input conductor.
An electrical circuit, comprising:
- a first input FET coupled to a second input FET forming a differential pair amplifier, the source of the first input FET coupled to a source of the second input FET, and the drain of the first input FET coupled to a drain of the second input FET.
- a gate load coupled to a gate of the first input FET;
- a drain load coupled to a drain of the first input FET, wherein the drain load comprises a drain capacitor coupled to the drain of the first input FET;
- a source load coupled to a source of the first input FET;
- a controllable variable current generator to provide a current to the source of the first input FET, biasing the source of the first input FET to a reference voltage;
- a first input conductor coupled to the gate of the first input FET and a input voltage signal including a variable input signal applied to the first input conductor;
- a second input conductor coupled to the gate of the second input FET, and a second input voltage signal applied to the second input conductor, the second input voltage including an inverted input signal of the first input voltage signal.
Dependencies are inferred from the claim text.