Security Circuit for Power Up
AssigneeIcera Inc.
InventorKevin Dewar
Life of this patent
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Abstract
A circuit and method for securing against non-reset of a device associated with the circuit, the circuit comprising: a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value; a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value; an inverter means arranged to invert only one of the first and second output values; and a comparator arranged to compare the inverted and non-inverted output values to produce a comparator output, wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions.
Claims14
A circuit for securing against non-reset of a device associated with the circuit, the circuit comprising:
- a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value;
- a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value;
- an inverter means arranged to invert only one of the first and second output values;
- and
- a comparator arranged to compare the inverted and non-inverted output values to produce a comparator output,
- wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions.
A method of resetting a circuit associated with a device, comprising the steps of:
- loading each of a first and second register which are subject to substantially the same operational conditions with the same multi-bit value;
- producing a first multi-bit output value related to the multi-bit value from the first register;
- producing a second multi-bit output value related to the multi-bit value from the second register;
- inverting only one of the first and second output values;
- and
- comparing the inverted and non-inverted output values to provide an indication that the device is in secure mode.
A method of indicating a secure state of a circuit associated with a device without resetting on power-up of the circuit, comprising the steps of:
- allowing a first register to settle to a first multi-bit value and produce a first multi-bit output value related to the first multi-bit value;
- allowing a second register to settle to a second multi-bit value and produce a second multi-bit output value related to the second multi-bit value;
- inverting only one of the first and second output values;
- and
- comparing the inverted and non-inverted output values to produce a comparator output,
- wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions and thereby tend to settle to the same multi-bit values.
A device comprising a circuit for securing against non-reset of a device associated with the circuit, the circuit comprising:
- a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value;
- a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value;
- an inverter means arranged to invert only one of the first and second output values;
- and
- a comparator arranged to compare the inverted and non-inverted output values to produce a comparator output,
- wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions.
Dependencies are inferred from the claim text.