Vertical soi trench sonos cell

A design structure embodied in a machine readable medium, the design structure comprising:

• a semiconductor-on-insulator substrate comprising a top semiconductor layer and a bottom semiconductor layer that are separated from each other by a buried insulating layer;
• at least one pair of vertical trench SONOS memory cells located within said semiconductor-on-insulator substrate, each vertical trench SONOS memory cell includes a source diffusion located beneath said vertical trench, a select gate channel located on one side of said vertical trench, an outdiffused/Si-containing bridge located above and in contact with said select gate channel, and a silicided doped region located adjacent to and in contact with an upper portion of said bridge, wherein said bridge is present within said top semiconductor layer, said buried insulating layer and said lower semiconductor layer;
• and
• a deep trench isolation region separating each pair of memory cells, wherein said deep trench isolation region has a depth that is below that of said source diffusion of each memory cell.