Moment computation algorithms in vlsi system
AssigneeLSI Corporation
InventorsWeiqing Guo, Sandeep Bhutani
Life of this patent
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Abstract
An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.
Claims13
A method for calculating moments for an interconnect circuit model, comprising the steps of:
- (a) creating at least one parasitic graph for the interconnect circuit model, wherein the at least one parasitic graph comprises a plurality of nodes;
- (b) determining if the at least one parasitic graph has been reduced;
- (c) reducing the at least one parasitic graph if the at least one parasitic graph has not been reduced, wherein the reducing comprises:
- (c1) performing a depth-first-search on the at least one parasitic graph,
- (c2) determining a degree of a deepest node with a smallest degree, wherein the node can have a degree of more than one,
- (c3) reducing the at least one parasitic graph by eliminating the node, and
- (c4) recursively performing the determining step (c2) and the reducing step (c3) until the depth-first-search completes;
- and
- (d) computing moments for the interconnect circuit model utilizing the reduced graph.
A computer readable medium with program instructions for calculating moments for an interconnect circuit model, comprising the instructions for:
- (a) creating at least one parasitic graph for the interconnect circuit model, wherein the at least one parasitic graph comprises a plurality of nodes;
- (b) determining if the at least one parasitic graph has been reduced;
- (c) reducing the at least one parasitic graph if the at least one parasitic graph has not been reduced, wherein the reducing comprises:
- (c1) performing a depth-first-search on the at least one parasitic graph,
- (c2) determining a degree of a deepest node with a smallest degree, wherein the node can have a degree of more than one,
- (c3) reducing the at least one parasitic graph by eliminating the node, and
- (c4) recursively performing the determining step (c2) and the reducing step (c3) until the depth-first-search completes;
- and
- (d) computing moments for the interconnect circuit model utilizing the reduced graph.
Dependencies are inferred from the claim text.