High-density, trench-based non-volatile random access sonos memory cells for soc applications

A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising:

• a semiconductor substrate including at least one array region that contains a plurality of trench structures having a depth from about 1 to about 2 μm, each trench structure including a lower portion comprising a select gate transistor having a channel located on vertical sidewalls of said trench structure, and an upper portion comprising a memory transistor including an oxide/nitride/oxide gate dielectric, wherein said select gate transistor comprises a select gate dielectric on bare sidewalls of each trench structure in said lower portion and a conductive fill material, wherein said source diffusion is the source of the select gate transistor and a diffusion of the memory transistor is the drain of the select transistor;
• a trench isolation region located between selected trench structures;
• a source diffusion located beneath a bottom wall of each trench structure, wherein said source diffusion is in contact with a diffusion of said memory transistor through said vertical select channel;
• and
• a select gate contact located on a surface of said select gate transistor, wherein said select gate contact is in contact with a first metal level.