Self-timed error correcting code evaluation system and method
AssigneeMicron Technology, Inc.
InventorJames Brian Johnson
Life of this patent
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Abstract
Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.
Claims25
In a memory system, a method of evaluating signals, comprising:
- receiving a plurality of signals;
- receiving signals corresponding to a transmitted error correcting code;
- calculating a part of a generated error correcting code from at least some of the received signals;
- completing the calculation of the generated error correcting code from the calculated part of the error correcting code;
- comparing the calculated error correcting code with the transmitted error correcting code;
- and
- if the calculated error correcting code matches the transmitted error correcting code, outputting at least some of the received signals asynchronously with any clock signal as the comparison is completed.
A method of evaluating signals in a memory system, comprising:
- receiving a plurality of signals;
- receiving a transmitted ECC value;
- providing the captured signals to a first set of logic gates;
- generating a partial sum of terms from at least some of the signals;
- latching the partial sum of the terms responsive to a first clock;
- providing the partial sum of terms to a second set of logic gates;
- generating an ECC value from the partial sum of terms;
- comparing the generated ECC value with the transmitted ECC value to generate a valid signal when the generated ECC value matches the calculated ECC value;
- and
- asynchronously outputting the plurality of signals responsive to the completion of comparing the generated ECC value to the transmitted ECC value if the generated ECC value matches the transmitted ECC value.
A logic path for accessing a memory array within a memory device, comprising:
- a first input operable to receive a plurality of bits, the plurality of bits including command bits and a transmitted ECC value;
- a static logic circuit coupled to the input, the static logic circuit operable to generate a partial sum of terms from at least some of the plurality of bits;
- a dynamic logic circuit coupled to the static logic circuit and being operable to receive the partial sum of terms and calculate an ECC value from the partial sum of terms, the dynamic logic circuit further operable to compare the calculated ECC value with the transmitted ECC value;
- and
- an ECC valid logic operable to asynchronously provide the command bits to the memory array when the calculated ECC value matches the transmitted ECC value.
A logic path in a memory device, comprising:
- an input operable to receive a packet containing a plurality of bits and a transmitted error correcting code value;
- a first set of logic gates coupled to the input and clocked by a first internal clock, the plurality of logic gates operable to generate a partial sum of terms from at least some of the plurality of bits;
- a second set of logic gates coupled to the first set of logic gates and clocked by a second internal clock, the second set of logic gates operable to calculate an error correcting code value and compare the calculated error correcting code with the transmitted error correcting code;
- and
- a delay circuit provided between the first internal clock signal and the second internal clock signal.
A memory device comprising:
- an array of memory cells;
- an addressing circuit operable to receive an address and to select a row or column of memory cells in the array responsive to receiving the address;
- a command decoder operable to generate control signals corresponding to a received memory command and to control operation of the memory device;
- a data path operable to transfer read data from the array of memory cells from the memory device and to transfer write data to the array of memory cells;
- and
- a logic path to access the array of memory cells, comprising:
- a first input operable to receive the address, memory command and write data and a transmitted ECC value;
- a static logic circuit coupled to the input, the static logic circuit operable to generate a partial sum of terms from the address, memory command and write data;
- and
- a dynamic logic circuit coupled to the static logic circuit and being operable to receive the partial sum of terms and calculate an ECC value from the partial sum of terms, the dynamic logic circuit further operable to compare the calculated ECC value with the transmitted ECC value;
- and
- a gating circuit coupled to the dynamic logic circuit and the first input, the gating circuit being operable to couple the received memory commands to the command decoder responsive to the calculated ECC value matching the transmitted ECC value.
Dependencies are inferred from the claim text.